1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and more particularly, to a method for manufacturing a semiconductor device capable of forming isolation in the bottom portion of a trench formed on a semiconductor substrate in a self-aligning manner.
2. Description of the Prior Art
Conventionally, in a semiconductor device such as an MOS (Metal Oxide Semiconductor) dynamic memory, a trench has been formed in an isolation region of a semiconductor substrate and three-dimensional charge storage capacitance utilizing a polysilicon film as an electrode has been embedded in the trench to compensate for decrease in two-dimensional charge storage capacitance caused by high integration of a memory cell.
A three-dimensional capacitor cell for such a large capacity dynamic memory is disclosed in, for example, an article by S. Nakajima et al., entitled "AN ISOLATION-MERGED VERTICAL CAPACITOR CELL FOR LARGE CAPACITY DRAM", International Electron Device Meeting, 1984 (IEDM 84), pp. 240-243.
FIGS. 1A to 1F are cross sectional views showing each main process in a method for manufacturing the conventional semiconductor device. Referring now to the drawings, description is made on the conventional semiconductor device.
Referring now to FIG. 1A, a trench 2 is formed on the major surface of a semiconductor substrate 1 by anisotropic etching. An oxide film 3 formed by thermal oxidation is deposited over the major surface of the semiconductor substrate 1 and the entire surface inside the trench 2 and then, a direct contact 4 is formed by etching a part of the oxide film 3. Furthermore, a polysilicon film 5 including ions of a conductivity type opposite to that of the semiconductor substrate 1 is deposited on the oxide film 3 and then, a diffusion layer 6 including ions of the conductivity type opposite to that of the semiconductor substrate 1 is formed in the semiconductor substrate 1 through the direct contact 4.
Referring now to FIG. 1B, a resist 7 is applied on the entire surface of the polysilicon film 5 including the inside of the trench 2.
Referring now to FIG. 1C, patterning is applied by exposure and development so that the resist 7 may be removed from the inside of the trench 2 and resist 7 may be left only on the planar portion of the semiconductor substrate 1.
Referring now to FIG. 1D, the polysilicon film 5 exposed in the bottom portion of the trench 2 is removed by anisotropic etching utilizing the resist 7 left in the planar portion of the semiconductor substrate 1 as a mask, so that the polysilicon film 5 is divided into two in the bottom portion of the trench 2.
Referring now to FIG. 1E, the resist 7 is removed from the planar portion of the semiconductor substrate 1.
Referring now to FIG. 1F, a thin oxide film 8 is formed by oxidizing the polysilicon film 5 and then, a polysilicon film 9 is deposited thereon. Thus, charge storage capacitance is formed between the polysilicon films 5 and 9.
As described in the foregoing, in the conventional method for manufacturing the semiconductor device, a trench is formed in an isolation region of the semiconductor substrate and three-dimensional charge storage capacitance is formed on the side wall of the trench, so that large charge storage capacitance can be maintained as a whole, although two-dimensional charge storage capacitance is decreased due to decrease in the area of each memory cell caused by high integration. In addition, in the semiconductor device (FIG. 1F) manufactured by the above described method, the charge storage capacitance, i.e. charges stored in the polysilicon film 5 is affected by electrons of electron hole pairs formed in the semiconductor substrate 1 along the range of alpha particles only through the direct contact 4. Therefore, charge collection efficiency of the polysilicon film 5 is low, so that a semiconductor device having a structure immune to soft errors can be obtained.
However, since the conventional semiconductor device is manufactured by the above described method, the resist 7 embedded inside the trench 2 is thicker than the resist 7 formed on the planar portion of the semiconductor substrate 1 as shown in FIG. 1B, so that the resist 7 is liable to be left without being removed from the inside of a trench 2 by exposure and development. When such offset of a resist mask occurs, the polysilicon film 5 in the bottom portion of the trench 2 can not be removed by anisotropic etching, so that it is very difficult to divide the polysilicon film 5 into two to form complete isolation.